FPGA-based Graph Neural Networks Accelerator Design

2022/02 - Present

• An FPGA-based overlay processor and a series of accelerator are proposed for Graph Neural Networks (GNNs), facilitating rapid end-to-end software reconfiguration across diverse GNN model accelerators.
• Optimized designs for sparse matrix multipliers are presented, encompassing symmetric sparse matrix multipliers and high bandwidth general sparse matrix multipliers.
• Publications:
  1. “ATE-GCN: An FPGA-based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization”, in DATE, 2025.
  2. “FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities”, in TRETS, 2024.
  3. “S-LGCN: Software-Hardware Co-Design for Accelerating LightGCN”, in DATE, 2024.
  4. “Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks”, in FPL & TRETS, 2023.
  5. “Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks”, in FPGA, 2023.
  6. “eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication,” in ISCAS, 2023.