About me
I’m under the advisement of Prof. Bruno da Silva and pursuing the Ph.D. degree in Engineering Sciences at the Vrije Universiteit Brussel. My research interests include domain-specific architecture and FPGA-based accelerators. From 2020 to 2023, I served as a Research Assistant with VeriMake Innovation Lab, Fudan University and Southeast University, respectively. I received my M.S. degree in Integrated Circuit Engineering from Fuzhou University in 2020, and the B.S. degree in Electronic Science and Technology from Southeast University Chengxian College in 2017.
You can find my CV here: Ruiqi Chen’s Curriculum Vitae.
You can contact me via Email or WeChat.
🔬 Research Interests
📰 Latest News
- 11/2024: I’m serving as a reviewer for the ISCAS 2025
- 11/2024: 🎉 Our work (ATE-GCN) is accepted by DATE 2025
- 07/2024: I’m serving as a reviewer for the APCCAS 2024
- 07/2024: I’m serving as a reviewer for the BIOCAS 2024
- 07/2024: 🎉 Our survey (FPGA-Based Sparse Matrix Multiplication Accelerators) is accepted by TRETS
- 04/2024: 🎉 Our work (Vina-FPGA-Cluster) is accepted by TBioCAS (Early Access)
- 11/2023: I’m serving as a reviewer for the ISCAS 2024
- 11/2023: 🎉 Our work is accepted by DATE 2024
- 07/2023: I’m serving as a reviewer for the BIOCAS 2023
- 05/2023: 🎉 Our works are accepted by FPL 2023
📃 Selected Publications
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool with High-Accuracy and Multi-Level Parallelism [PDF]
Ming Ling, Zhihao Feng, Ruiqi Chen, et al
IEEE Transactions on Biomedical Circuits and Systems, 2024, 18(6): 1321-1337.
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities [PDF]
Yajing Liu, Ruiqi Chen, Shuyang Li, et al
ACM Transactions on Reconfigurable Technology and Systems, 2024, 17(4), Article 59 (November 2024): 1-37.
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks [PDF]
Ruiqi Chen, Haoyang Zhang, Shun Li, et al
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication [PDF]
Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, et al
2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism [PDF]
Ming Ling, Qingde Lin, Ruiqi Chen, et al
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 31(4): 484-497.
Accelerating AutoDock VINA with GPUs [PDF]
Shidi Tang, Ruiqi Chen, Ming Ling, et al
Molecules, 2022, 27(9): 3041.